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ace2 5ac512g spi nor flash ver 1.1 1 description t he ace25ac512g is 512k - bit serial flash supports the standard serial peripheral interface (spi). spi clock frequency of up to 120mhz is supported for fast read command. features ? 512k - bit serial flash 256 bytes per programmable page ? standard spi standard spi: sclk, cs#, si, so, ? high speed clock frequency 120mhz for fast read with 30pf load ? program/erase speed page program time: 1.5ms typical sector erase time: 150ms typical block erase time: 0.8s typical chip erase time: 6s/3s typic ? flexible a rchitecture sector of 4k - byte block of 64k - byte ? low power consumption 10ma maximum active current 5ua maximum standby current ? single power supply voltage: full voltage range:2.7~3.6v ? minimum 100,000 program/erase cycle absolute maximum ratings parameter v alue unit ambient operating temperature - 40 to 85 storage temperature - 65 to 150 output short circuit current 200 ma applied input/output voltage - 0.5 to 4.0 v vcc - 0.5 to 4.0 v
ace2 5ac512g spi nor flash ver 1.1 2 packaging type dip - 8 sop - 8 sop - 8 l tssop - 8 pi n configurations pin name i/o functions cs# i chip select input so o data output vss ground si i data input sclk i serial clock input vcc power supply ordering information ace2 5ac512g xx + x h pb - free u: tube t : tape and reel dp : dip - 8 fm : sop - 8 fml : sop - 8l ( 208mil) tm : tssop - 8 halogen - free
ace2 5ac512g spi nor flash ver 1.1 3 block diagram unifo rm block sector architecture ace25ac512g 64k bytes block sector architecture block sector address range 0 15 0 0 f000h 0 0 ffffh device operation the ace25ac512g features a s erial peripheral interface on 4 signals bus: serial clock (sclk), chip select (cs#), serial data input (si) and serial data output (so). both spi bus mode 0 and 3 are supported. input data is latched on the rising edge of sclk and data shifts out on the fa lling edge of sclk.
ace2 5ac512g spi nor flash ver 1.1 4 d ata protection the ace25ac512g provides the following data protection methods: write enable (wren) command: the wren command is set the write enable latch bit (wel). the wel bit will return to reset by the following situation: ? pow er - up ? write disable (wrdi) ? write status register (wrsr) ? page program (pp) ? sector erase (se) / block erase (be) / chip erase (ce) software protection mode: ? srwd=0, the block protect (bp2, bp1, bp0) bits define the section of the memory array that can be rea d but not change srwd=1, the write status register (wrsr) instruction is no longer accepted for execution and the ? srwd bit and block protect bits (bp2, bp1, bp0) are read only. table 1. ace25ac512g protected area sizes status bit protect level protect bloc k bp2 bp1 bp0 0 0 0 0(none) none 0 0 1 1 (1 block) block 7 0 1 0 2 (2 blocks) block 6 - 7 0 1 1 3 (4 blocks) block 4 - 7 1 0 0 4 (8 blocks) all 1 0 1 5 (all) all 1 1 0 6 (all) all 1 1 1 7 (all) all
ace2 5ac512g spi nor flash ver 1.1 5 status register s7 s6 s5 s4 s3 s2 s1 s0 srwd reserved reserved bp2 bp1 bp0 wel wip the status and control bits of the status register are as follows: wip bit. the write in progress (wip) bit indicates whether the memory is busy in program/erase/write status register progress. when wip bit se ts to 1, the device is busy in program/erase/write status register progress. when wip bit sets 0, the device is not in program, erase or write status register . wel bit. the write enable latch (wel) bit indicates the status of the internal write enable latc h. when set to 1, the internal write enable latch is set. when set to 0, the internal write enable latch is reset and no write status register, progra m or erase command is accepted. bp2, bp1, bp0 bits. the block protect (bp2, bp1, bp0) bits are non - volatil e. they define the size of the area to be software protected against program and erase commands. these bits are written with the write status register (wrsr) command. when the block protect (bp2, bp1, bp0) bits are set to 1, the relevant memory area (as de fined in table1) becomes protected against page program (pp), sector erase (se) and block erase (be) commands. chip erase command will be ignored if one or more of the block protect (bp2, bp1, bp0) bits are 1. srwd bit. the status register write disable ( srwd) bit is a non - volatile one time program (otp) bit in the status register that provide another software protection. once it is set to 1, the write status register (wrsr) instruction is no longer accepted and the srwd bit and block protect bits (bp2, bp 1, bp0) are read only. srwd status register memory 0 status register can be written in (wel bit is set to "1") and the srwd, bp2 - bp0 bits can be changed the protected area cannot be program or erase 1 the srwd, bp2 - bp0 of status register bits cannot be c hanged the protected area cannot be program or erase
ace2 5ac512g spi nor flash ver 1.1 6 commands description all commands, addresses and data are shifted in and out of the device, beginning with the most significant bit on the first rising edge of sclk after cs# is driven low. then, the one - byte command code must be shifted in to the device, most significant bit first on si, each bit being latched on the rising edges of sclk. see table2, every command sequence starts with a one - byte command code. depending on the command, this might be followed by address bytes, or by data bytes, or by both or none. cs# must be driven high after the last bit of the command sequence has been shifted in. for the command of read, fast read, read status register, and read device id, the shifted - in command sequence is followed by a data - out sequence. cs# can be driven high after any bit of the data - out sequence is being shifted out. for the command of page program, sector erase, block erase, chip erase, write status register, write enable, write disable, cs # must be driven high exactly at a byte boundary, otherwise the command is rejected. that is cs# must driven high when the number of clock pulses after cs# being driven low is an exact multiple of eight. for page program, if at any time the input byte is n ot a full byte, nothing will happen and wel will not be reset. table2. commands command name byte1 byte2 byte3 byte4 byte5 byte6 n - bytes write enable 06h write disable 04h read status register 05h (s7 - s0) (continuous) write status regi ster 01h (s7 - s0) (continuous) read data 03h a23 - a16 a15 - a8 a7 - a0 (d7 - d0) (next byte) (continuous) fast read 0bh a23 - a16 a15 - a8 a7 - a0 dummy (d7 - d0) (continuous) page program 02h a23 - a16 a15 - a8 a7 - a0 (d7 - d0) (next byte) sector erase 20h a23 - a16 a15 - a8 a7 - a0 block erase d8h a23 - a16 a15 - a8 a7 - a0 chip erase c7/60h manufacturer/device id 90h dummy dummy 00h (mid7 - mid0) (did7 - did0) (continuous) read identification 9fh (mid7 - mid0) (jdid15 - jdi d8) (jdid7 - jdid 0) (continuous)
ace2 5ac512g spi nor flash ver 1.1 7 id definiti ons operation code m7 - m0 id15 - id8 id7 - id0 9fh 0e 40 13 90h 0e 12 write enable (wren) (06h) the write enable (wren) command is for setting the write enable latch (wel) bit. the write enable latch (wel) bit must be set prior to every page program (pp), sector era se (se), block erase (be), chip erase (ce) and write status register (wrsr) command. the write enable (wren) command sequence: cs# goes low send write enable command cs# goes high. write disable (wrdi) (04h) the write disable command is for resetting the write enable latch (wel) bit. the write disable command sequence: cs# goes low send write disable command cs# goes high. the wel bit is re set by following condition: power - up and upon completion of the write status register, page program, sector erase, block erase and chip erase commands. figure1. write enable sequence diagram figure2. write disable sequence diagram
ace2 5ac512g spi nor flash ver 1.1 8 read status register (rdsr) (05h) the read status register (rdsr) command is for reading the status register. the status register may be read at any time, even while a program, erase or write status register cycle is in progress. when one of these cycles is in progress, it is recommended to check the write in progress (wip) bit before sending a ne w command to the device. it is also possible to read the status register continuously. write status register (wrsr) (01h) the write status register (wrsr) command allows new values to be written to the status register. before it can be accepted, a write enable (wren) command must previously have been executed. after the write enable (wren) command has been decoded and executed, the device sets the write enable latch (wel). the write status register (wrsr) command has no effect on s6, s5, s1 and s0 of the status register. cs# must be driven high after the eighth bit of the data byte has been latched in. if not, the write status register (wrsr) command is not executed. as soon as cs# is driven high, the self - timed write status register cycle (whose duration is tw) is initiated. while the write status register cycle is in progress, the status register may be read to check the value of the write in progress (wip) bit. the write in progress (wip) bit is 1 during the self - timed write status register cycle, and is 0 when it is completed. when the cycle is completed, the write enable latch (wel) is reset. the write status register (wrsr) command allows the user to change the values of the block protect (bp2, bp1, bp0) bits, to define the size of the area that is to be treated as read - only, as defined in table1.1 and 1.2. the status register write disable (srwd) bit is a non - volatile one time program(otp) bit, the write status register (wrsr) command allows the user to set the status register write disable (srwd) bit to 1. the status register write disable (srwd) bit allow the device to be put in another software protected mode. once the srwd bit is set to 1, the write status register (wrsr) command is not executed, and the srwd bit and block protect bits (bp2, bp1, bp 0) are read only. figure3. read status register sequence diagram figure 4. write status register sequence diagram
ace2 5ac512g spi nor flash ver 1.1 9 read data bytes (read) (03h) the read data bytes (read) command is followed by a 3 - byte address (a23 - a0), each bit being latched - in during the rising edge of sclk. then the memory content, at that address, is shifted out on so , each bit being shifted out, at a max frequency fr, during the falling edge of sclk. the first byte addressed can be at any location. the address is automatically incremented to the next higher address after each byte of data is shifted out. therefore, th e whole memory can be read with a single read data bytes (read) command. during an erase, program or write cycle, read data byte (read) command will be rejected without affecting the cycle in progress. read data bytes at higher speed (fast read) (0bh) t he read data bytes at higher speed (fast read) command is for quickly reading data out. it is followed by a 3 - byte address (a23 - a0) and a dummy byte, each bit being latched - in during the rising edge of sclk. then the memory content, at that address, is shi fted out on so, each bit being shifted out, at a max frequency f c , during the falling edge of sclk. the first byte address can be at any location. the address is automatically incremented to the next higher address after each byte of data is shifted out. figure5. read data bytes sequence diagram figure6. read data bytes at higher speed sequence diagram
ace2 5ac512g spi nor flash ver 1.1 10 page program (pp) (02h) the page program (pp) command is for programming the memory. a write enable (wren) command must previously have been executed to set the write enable latch (wel) bit before sending the page program command. the page program (pp) c ommand is entered by driving cs# low, followed by the command code, three address bytes and at least one data byte on si. if the 8 least significant address bits (a7 - a0) are not all zero, all transmitted data that goes beyond the end of the current page ar e programmed from the start address of the same page (from the address whose 8 least significant bits (a7 - a0) are all zero). cs# must be driven low for the entire duration of the sequence. the page program command sequence: cs# goes low sending page progra m command - byte address on si the command sequence is shown in figure7. if more than 256 bytes are sent to the device, previously latched data are discarded and the last 256 data bytes are guaranteed to be programmed corr ectly within the same page. if less than 256 data bytes are sent to device, they are correctly programmed at the requested addresses without having any effects on the other bytes of the same page. cs# must be driven high after the eighth bit of the last da ta byte has been latched in; otherwise the page program (pp) command is not executed. as soon as cs# is driven high, the self - timed page program cycle (whose duration is tpp) is initiated. while the page program cycle is in progress, the status register ma y be read to check the value of the write in progress (wip) bit. the write in progress (wip) bit is 1 during the self - timed page program cycle, and is 0 when it is completed. write enable latch (wel) bit is reset to 0 at the end of the page program cycle.. page program (pp) command applied to a page which is protected by the block protect (bp2, bp 1, bp0) bit (see table1 ) is not executed. figure7. page program sequence diagram
ace2 5ac512g spi nor flash ver 1.1 11 sector erase (se) (20h) the sector erase (se) command is for erasing the all data of the chosen sector. a write ena ble (wren) command must previously have been executed to set the write enable latch (wel) bit. the sector erase (se) command is entered by driving cs# low, followed by the command code, and 3 - address byte on si. any address inside the sector is a valid add ress for the sector erase (se) command. cs# must be driven low for the entire duration of the sequence. the sector erase command sequence: cs# goes low sending sector erase command - byte address eighth bit of the last address byte has been latched in; otherwise the sector erase (se) command is not executed. as soon as cs# is driven high , the self - timed sector erase cycle (whose duration is tse) is initiated. while the sector erase cycle is in progress, the status register may be read to check the value of the write in progress (wip) bit. the write in progress (wip) bit is 1 during the s elf - timed sector erase cycle, and is 0 when it is completed. write enable latch (wel) bit is reset to 0 at the end of the sector erase cycle. sector erase (se) command applied to a sector which is protected by the block protect (bp2, bp 1, bp0) bit (see tab le1 ) is not executed. block erase (be) (d8h) the block erase (be) command is for erasing the all data of the chosen block. a write enable (wren) command must previously have been executed to set the write enable latch (wel) bit. the block erase (be) comm and is entered by driving cs# low, followed by the command code, and three address bytes on si. any address inside the block is a valid address for the block erase (be) command. cs# must be driven low for the entire duration of the sequence. the block er ase command sequence: cs# goes low send block erase command 3 - byte address on e driven high after the eighth bit of the last address byte has been latched in; otherwise the block erase ( be) command is not executed. as soon as cs# is driven high, the self - timed block erase cycle (whose duration is tbe) is initiated. while the block erase cycle is in progress, the status register may be read to check the value of the write in progress (wip) bit. the write in progress (wip) bit is 1 during the self - timed block erase cycle, and is 0 when it is completed. write enable latch (wel) bit is reset to 0 at the end of the block erase cycle. block erase (be) commands applied to a block which is protect ed by the block protect (bp2, bp1, bp0) bits (see table1 ) is not executed. figure8. sector erase sequence diagram figure9. block erase sequen ce diagram
ace2 5ac512g spi nor flash ver 1.1 12 chip erase (ce) (60/c7h) the chip erase (ce) command is for erasing the all data of the chip. a write enable (wren) command must previously have been executed to set the write enab le latch (wel) bit .the chip erase (ce) command is entered by driving cs# low, followed by the command code on serial data input (si). cs# must be driven low for the entire duration of the sequence. the chip erase command sequence: cs# goes low send chip erase command cs# goes high. the command sequence is shown in figure10. cs# must be driven high after the eighth bit of the command code has been latched in, otherwise the chip erase command is not executed. as soon as cs# is driven high, the self - timed ch ip erase cycle (whose duration is tce) is initiated. while the chip erase cycle is in progress, the status register may be read to check the value of the write in progress (wip) bit. the write in progress (wip) bit is 1 during the self - timed chip erase cyc le, and is 0 when it is completed. write enable latch (wel) bit is reset to 0 at the end of the chip erase cycle. the chip erase (ce) command is ignored if one or more sectors are protected by (bp2, bp1, bp0) bits. read manufacture id/ device id (rems) ( 90h) the read manufacturer/device id command is for reading both the jedec assigned manufacturer id and the specific device id. the command is initiated by driving the cs# pin low and shifting the command code 90h followed by a 24 - bit address (a23 - a0) of 000000h. after which, the manufacturer id and the device id are shifted out on the falling edge of sclk with most significant bit (msb) first as shown in figure11. if the 24 - bit address is initially set to 000001h, the device id will be read first . figure10. chip erase sequence diagram figure11. read manufacture id/ device id sequence diagram
ace2 5ac512g spi nor flash ver 1.1 13 read identification (rdid) (9fh) the read identification (rdid) command allows the 8 - bit manufacturer identification to be read, followed by two bytes of device identification. the device identification indicates the memory type in the first b yte, and the memory capacity of the device in the second byte. any read identification (rdid) command while an erase or program cycle is in progress, is not decoded, and has no effect on the cycle that is in progress. the device is first selected by drivin g cs# to low. then, the 8 - bit command code for the command is shifted in. this is followed by the 24 - bit device identification, stored in the memory, being shifted out on serial data output, each bit being shifted out during the falling edge of serial cloc k. the command sequence is shown in figure12. the read identification (rdid) command is terminated by driving cs# to high at any time during data output. after cs# is driven high, the device returns to standby mode and awaits for new command. figure12. read identification id sequence diagram
ace2 5ac512g spi nor flash ver 1.1 14 electrical characteristics power - on timing table3. power - up timing and write inhibit threshold symbol parameter min max unit t vsl vcc(min) to cs# low 10 us t puw time delay before write instruction 1 10 ms v wi write inhibit voltage 1 2.5 v initial delivery state the device is delivered with the memory array erased: all bits are set to 1(each byte contains ffh).the status register contains 00h (all status register bits are 0). data retention and endurance parameter test condition min unit minimum pattern data retention time 150 10 years 125 20 years erase/program endurance - 40 to 85 100k cycles latch up characteristics parameter min max input voltage respect to vss on i/o pins - 1.0v vcc+1.0v vcc current - 100ma 100ma
ace2 5ac512g spi nor flash ver 1.1 15 capacitance measurement condition symbol para meter min typ max unit conditions c in input capacitance 6 pf vin=0v c out output capacitance 8 pf vout=0v c l load capacitance 30 pf input rise and fall time 5 ns input pulse voltage 0.1vcc to 0.8vcc v input timing reference voltage 0.2vcc to 0.7vcc v output timing reference voltage 0.5vcc v maximum negative overshoot waveform maximum positive overshoot waveform figure13. input t est waveform and measurement leve l
ace2 5ac512g spi nor flash ver 1.1 16 d c characteristics (t= - 40 ~85 ,vcc=2.7~3.6v) symbol parameter test condition min. typ max. unit i li input leakage current 2 a a a
ace2 5ac512g spi nor flash ver 1.1 17 ac characteristics (t= - 40 ~85 ,vcc=2.7~3.6v cl=30pf) symbol parameter min. typ max. unit f c serial clock frequency for:fast read(0bh), dc 120 mhz f r serial clock frequency for:read(03h) dc 40 mhz t clh serial clock high time 4 ns t cll serial clock low time 4 ns t clch se rial clock rise time(slew rate) 0.2 v/ns t chcl serial clock fall time(slew rate) 0.2 v/ns t slch cs# active setup time 5 ns t chsh cs# active hold time 5 ns t shch cs# not active setup time 5 ns t chsl cs# not active hold time 5 ns t shsl cs# high time (read/write) 20 ns t shqz output disable time 6 ns t clqx output hold time 1 ns t dvch data in setup time 2 ns t chdx data in hold time 2 ns t hlch hold# low setup time(relative to clock) 5 ns t hhch hold# high setup time(relative to clock) 5 ns t chhl hold# high hold time(relative to clock) 5 ns t chhh hold# low hold time(relative to clock) 5 ns t hlqz hold# low to high - z output 6 ns t hhqx hold# low to low - z output 6 ns t clqv clock low to output valid 6.5 ns t whsl write protect setup time before cs# low 20 ns t shwl write protect hold time after cs# high 100 ns t res2 cs# high to standby mode with electronic signature read 0.1 us t w write status register cycle time 50 100 ms t pp page programming time 1.5 2 ms t se sector erase time 150 300 ms t be block erase time 0.8 1.5 s t ce chip erase time 6 10 s
ace2 5ac512g spi nor flash ver 1.1 18 figure14. serial input timing figure15. output timing
ace2 5ac512g spi nor flash ver 1.1 19 packaging information dip - 8 symbol dimensions in millimeters dimensions in inches min max min max a 3.710 4.310 0.146 0.170 a1 0.510 0.020 a2 3.200 3.600 0.126 0.142 b 0.380 0.570 0.015 0.022 b1 1.524 bsc 0.060 bsc c 0.204 0.360 0.008 0.014 d 9.000 9.400 0.354 0.370 e 6.200 6.600 0.244 0.260 e1 7.320 7.920 0.288 0.312 e 2.540 (bsc) 0.100 bsc l 3.000 3.600 0.118 0.142 e2 8.400 9.000 0.331 0.354
ace2 5ac512g spi nor flash ver 1.1 20 packaging information sop - 8 symbol dimensions in millimeters dimensions in inches min max min max a 1.350 1.750 0.053 0.069 a1 0.100 0.250 0.004 0.010 a2 1.350 1.550 0.053 0.061 b 0.330 0.5 10 0.013 0.020 c 0.170 0.250 0.006 0.010 d 4.700 5.100 0.185 0.200 e 3.800 4.000 0.150 0.157 e1 5.800 6.200 0.228 0.244 e 1.270 (bsc) 0.050 (bsc) l 0.400 1.270 0.016 0.050 0 8 0 8
ace2 5ac512g spi nor flash ver 1.1 21 packaging information sop - 8l ( 208mil) symbol dimensions in millimeters dimensions in inches min max min max a 2.150 0.085 a1 0.050 0.250 0.002 0.010 a2 1.700 1.900 0.067 0.075 b 0.350 0.500 0.014 0.020 c 0.100 0.250 0.004 0.010 d 5.130 5.330 0.202 0.210 e 7.700 8.100 0.303 0.319 e1 5.180 5.380 0.204 0.212 e 1.270 (bsc) 0.050 (bsc) l 0. 5 00 0.85 0 0.0 20 0.0 33 0 8 0 8
ace2 5ac512g spi nor flash ver 1.1 22 packaging information ts sop - 8 symbol dimensions in millimeters dimensions in inches min max min max d 2.900 3.100 0.114 0.122 e 4.300 4.500 0.169 0.177 b 0.190 0.300 0.007 0.012 c 0.090 0.200 0.004 0.008 e1 6.250 6.550 0.246 0.258 a 1. 2 00 0.04 7 a2 0.800 1.000 0.031 0.039 a1 0.0 5 0 0.150 0.00 2 0.006 e 0.65 (bsc) 0.026 (bsc) l 0.500 0.700 0.020 0.028 h 0.25 (typ) 0.01 (typ) 1 7 1 7
ace2 5ac512g spi nor flash ver 1.1 23 notes ace does not assume any responsibility for use as critical components in life support devices or systems without the express written approval of the president and general counsel of ace elect ronics co., ltd. as sued herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and shoes failure to perform when properly used in accordance with instructi ons for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. a critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failur e of the life support device or system, or to affect its safety or effectiveness. ace technology co., ltd. http://www.ace - ele.com/

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